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DATA SHEET
MOS INTEGRATED CIRCUIT
mPD78011B, 78012B, 78013, 78014
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The mPD78011B/78012B/78013/78014 are the prodcts in the mPD78014 subseries within the 78K/0 Series. The mPD78011B/78012B/78013/78014 have 8-bit resolution A/D converter, timer, serial interface, interrupt control, and many other peripheral hardware functions. A one-time PROM or EPROM product mPD78P014 capable of operating in the same power supply voltage range as of the mask ROM product and other development tools are also provided.
Functions are described in detail in the following User's Manual, which should be read when carring out design work. mPD78014, 78014Y Series User's Manual: IEU-1343
FEATURES
Y Large on-chip ROM & RAM
Item Product Name mPD78011B mPD78012B mPD78013 mPD78014 Data Memory Internal HighSpeed RAM 512 bytes Package Buffer RAM 32 bytes Y 64-pin plastic shrink DIP (750 mil) Y 64-pin plastic QFP (n14 mm) 1024bytes
Program Memory (ROM) 8K bytes 16K bytes 24K bytes 32K bytes
Y Y Y Y Y Y Y
External memory expansion space : 64K bytes Instruction execution time can be varied from high-speed (0.4 ms) to ultra-low-speed (122 ms) I/O ports: 53 (N-ch open-drain : 4) 8-bit resolution A/D converter : 8 channels Serial interface : 2 channels Timer : 5 channels Operating voltage range : 2.7 to 6.0 V
Application
Telephone, VCR, audio, camera, home appliances, etc.
The information in this document is subject to change without notice. Document No. IC-3179D (O.D.No. IC-8201F) Date Published January 1995 P Printed in Japan
The mark H shows major revised points.
(c)
1992
mPD78011B, 78012B, 78013, 78014
ORDERING INFORMATION
Ordering Code mPD78011BCW- mPD78011BGC--AB8 mPD78012BCW- mPD78012GC--AB8 mPD78013CW- mPD78013GC--AB8 mPD78014CW- mPD78014GC--AB8 Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (n14 mm) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (n14 mm) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (n14 mm) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (n14 mm) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard
Remarks
indicates ROM code No.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
H
78K/0 SERIES DEVELOPMENT
PD78078Y SubSeries PD78064Y SubSeries
Products under Development
Products in Volume Production
PD78078 SubSeries
100-pin package 8-bit timer/event counter added External expansion function enhanced
PD78064 SubSeries
100-pin package LCD controller/driver, UART added 16-bit timer/event counter function enhanced
Y series products are compatible with I2C bus.
PD78054Y SubSeries PD78054 SubSeries
80-pin package UART, D/A converter, Real-time output port added 16-bit timer/event counter function enhanced
PD78098 SubSeries
80-pin package IEBusTM controller added
PD78018FY SubSeries PD78014Y SubSeries PD78014 SubSeries PD78018F SubSeries
64-pin package Low-voltage, high-speed operation possible
PD78083 SubSeries
42/44-pin package UART, A/D converter, 8-bit timer/event counter function enhanced
64-pin package A/D converter, 16 bit-timer/event counter function, SIO with automatic transmit/receive function added Multiplication/division instruction added PD78044A SubSeries
PD780208 SubSeries
100-pin package FIP controller/driver function enhanced
PD78044 SubSeries
80-pin package Automatic transmit/receive function added 6-bit up/down counter added FIP controller/driver function enhanced
PD78024 SubSeries PD78002Y SubSeries PD78002 SubSeries
64-pin package 64-pin package A/D converter, 16 bit-timer/event counter, FIB(R) controller/driver, Multiplication/division instruction added
2
mPD78011B, 78012B, 78013, 78014
OVERVIEW OF FUNCTION (1/2)
Item Product Name ROM Internal highspeed RAM Buffer RAM 8K bytes 512 bytes 32 bytes 64K bytes 8 bits 32 registers (8 bits 8 registers 4 banks) On-chip instruction execution time cycle modification function 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 10.0 MHz operation) 122 ms (at 32.768 kHz operation) * * * * 16-bit operation Multiplication/division (8 bits 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. : 53 : 02 : 47 : 04 16K bytes 24K bytes 1024 bytes 32K bytes mPD78011B mPD78012B mPD78013 mPD78014
Internal memory
Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction set
I/O ports
Total * CMOS input * CMOS I/O * N-channel open-drain I/O (15 V withstand voltage)
A/D converter
* 8-bit resolution 8 channels * Operable over a wide power supply voltage range: VDD = 2.7 to 6.0 V * 3-wire/SBI/2-wire mode selectable: 1 channel * 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel * * * * 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels Watch timer : 1 channel Watchdog timer : 1 channel
Serial interface
Timer
Timer output Clock output
3 (14-bit PWM output 1) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation), 32.768 kHz (at subsystem clock 32.768 kHz operation) 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation) Internal : 8 External: 4 Internal : 1
Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt
Internal : 1
3
mPD78011B, 78012B, 78013, 78014
OVERVIEW OF FUNCTION (2/2)
Item Product Name Test input mPD78011B Internal : 1 External : 1 VDD = 2.7 to 6.0 V -40 to +85C * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (n14 mm) mPD78012B mPD78013 mPD78014
Operating voltage range Operating temperature range Package
4
mPD78011B, 78012B, 78013, 78014
CONTENTS
1. 2. 3. PIN CONFIGURATION (TOP VIEW) ............................................................................................................. 6 BLOCK DIAGRAM .......................................................................................................................................... 9 PIN FUNCTIONS ............................................................................................................................................. 10
3.1 PORT PINS ................................................................................................................................................ 10 3.2 OTHER PORTS ........................................................................................................................................... 11 3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ............................................. 13
4. 5.
MEMORY SPACE ........................................................................................................................................... 16 PERIPHEL HARDWARE FUNCTION FEATURES ....................................................................................... 17
5.1 5.2 5.3 5.4 5.5 5.6 5.7 PORTS ....................................................................................................................................................... CLOCK GENERATOR ................................................................................................................................. TIMER/EVENT COUNTER ......................................................................................................................... CLOCK OUTPUT CONTROL CIRCUIT ........................................................................................................ BUZZER OUTPUT CONTROL CIRCUIT ...................................................................................................... A/D CONVERTOR ...................................................................................................................................... SERIAL INTERFACES ................................................................................................................................. 17 18 19 22 22 23 24
6.
INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................................. 26
6.1 INTERRUPT FUNCTIONS .......................................................................................................................... 26 6.2 TEST FUNCTIONS ..................................................................................................................................... 29
7. 8. 9.
EXTERNAL DEVICE EXPANTION FUNCTIONS ......................................................................................... 30 STANDBY FUNCTIONS ................................................................................................................................. 30 RESET FUNCTIONS ....................................................................................................................................... 30
10. INSTRUCTION SET ........................................................................................................................................ 31 11. ELECTRICAL SPECIFICATIONS .................................................................................................................... 34 12. CHARACTERISTIC CURVE (REFERENCE VALUES) .................................................................................. 58 13. PACKAGE INFORMATION ............................................................................................................................ 63 14. RECOMMENDED SOLDERING CONDITIONS ........................................................................................... 67 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................................... 69 APPENDIX B. RELATED DOCUMENTS ............................................................................................................... 71
5
mPD78011B, 78012B, 78013, 78014
1. PIN CONFIGURATION (Top View)
64-Pin Plastic Shrink DIP (750 mil)
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVREF AVDD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
mPD78011BCW- , mPD78012BCW- mPD78013CW- , mPD78014CW-
Caution
1. Always connect the IC (Internally Connected) pin to VSS directly. 2. Always connect the AVDD pin to VDD. 3. Always connect the AVSS pin to VSS.
6
mPD78011B, 78012B, 78013, 78014
64-Pin Plastic QFP (n14 mm)
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60
P61
P62
P63
Caution
1. Always connect the IC (Internally Connected) pin to VSS directly. 2. Always connect the AVDD pin to VDD. 3. Always connect the AVSS pin to VSS.
P65/WR
P64/RD
VSS
P12/ANI2
P21/SO1
P23/STB
P20/SI1
AVREF
AVDD
mPD78011BGC- -AB8 mPD78012BGC- -AB8 mPD78013GC- -AB8 mPD78014GC- -AB8
7
mPD78011B, 78012B, 78013, 78014
P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 INTP0 to INTP3 TI0 to TI2 TO0 to TO2 SB0, SB1 SI0, SI1 SO0, SO1 SCK0, SCK1 PCL BUZ STB BUSY
: : : : : : : : : : : : : : : : : :
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Interrupt From Peripherals Timer Input Timer Output Serial Bus Serial Input Serial Output Serial Clock Programmable Clock Buzzer Clock Strobe Busy
AD0 to AD7 A8 to A15 RD WR WAIT ASTB X1, X2 XT1, XT2 RESET ANI0 to ANI7 AVDD AVSS AVREF VDD VSS IC
: : : : : : : : : : : : : : : :
Address/Data Bus Address Bus Read Strobe Write Strobe Wait Address Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected
8
2. BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00
16-bit TIMER/ EVENT COUNTER
PROGRAM COUNTER
PORT0
P00 P01-P03 P04
TO1/P31 TI1/P33
8-bit TIMER/ EVENT COUNTER 1 ROM PROGRAM MEMORY GENERAL REG. DECODE AND CONTROL
PORT1
P10-P17
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER 2
PORT2 RAM DATA MEMORY PORT3
P20-P27
P30-P37
WATCHDOG TIMER
PORT4 WATCH TIMER
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24
SERIAL INTERFACE 0
ALU
PSW
SP
PORT5
P50-P57
PORT6
P60-P67
mPD78011B, 78012B, 78013, 78014
SERIAL INTERFACE 1
BUZZER OUTPUT
CLOCK OUTPUT CONTROL
CLOCK DIVIDER
CLOCK GENERATOR SUB MAIN
STAND BY CONTROL
AD0/P40AD7/P47 A8/P50A15/P57
ANI0/P10 -ANI7/P17 AVDD AVSS AVREF INTP0/P00 -INTP3/P03
A/D CONVERTER
BUZ/P36
PCL/P35
P04/XT1 XT2
X1 X2
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67
INTERRUPT CONTROL
RESET VDD
VSS
IC
Remarks 9
Internal ROM & RAM capacity varies depending on the product.
mPD78011B, 78012B, 78013, 78014
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
I/O Input Input/ output Port 0 5-bit I/O port Input only Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software.*2 Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Function After Reset Input Input DualFunction Pin INTP0/TI0 INTP1 INTP2 INTP3 Input Input/ output Input Input XT1 ANI0 to ANI7
Pin Name P00 P01 P02 P03 P04*1 P10 to P17
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
Input/ output
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 3 8-bit input/output port. Input/output can be specified in 1-bit units. When used as an input port, pull-up resistor can be used by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Input/ output
Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
* 1. 2.
When using the P04/XT1 pins as an input port, set 1 to bit 6 (REC) of the processor control register. Do not use the on-chip feedback register of the subsystem clock oscillator. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, pull-up resistor is automatically unused.
10
mPD78011B, 78012B, 78013, 78014
3.1
PORT PINS (2/2)
I/O Input/ output Function Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Port 6 8-bit input/output port. Input/output can be specified bit-wise. After Reset Input DualFunction Pin A8 to A15
Pin Name P50 to P57
P60 P61 P62 P63 P64 P65 P66 P67
Input/ output
N-ch open-drain input/output port. Input On-chip pull-up resistor can be specified by mask option. LED can be driven directly. RD WR WAIT ASTB
When used as an input port, pull-up resistor can be used by software.
Caution
When pull-up resistors are not used (specified by mask option), the low-level input leak current increases with -200 mA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low-level is input to the pin. 2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode register (PM6).
3.2
OTHER PORTS (1/2)
I/O Input Function External interrupt input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. Falling edge detection external interrupt input. Input Serial interface serial data input. Input After Reset Input DualFunction Pin P00/TI0 P01 P02 P03 P25/SB0 P20 Output Serial interface serial data output. Input P26/SB1 P21 Input /output Input /output Output Input Serial interface serial data input/output. Input P25/SI0 P26/SO0 Serial interface serial clock input/output. Input P27 P22 Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Input Input P23 P24
Pin Name INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB BUSY
11
mPD78011B, 78012B, 78013, 78014
3.2
OTHER PORTS (2/2)
DualFunction Pin P00/INTP0 P33 P34 Input P30 P31 P32 Output Output Input /output Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data bus at external memory expansion. High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output. Input Output Wait insertion at external memory access. Strobe output which latches the address information output at port 4 and port 5 to access external memory. A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply. Connected to VDD. A/D converter ground potential. Connected to VSS. System reset input. Main system clock oscillation crystal connection. Input Input Input Input Input Input Input P35 P36 P40 to P47 P50 to P57 P64 P65 P66 P67
Pin Name TI0 TI1 TI2 TO0 TO1 TO2 PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB
I/O Input
Function External count clock input to 16-bit timer (TM0). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2).
After Reset Input
Output
16-bit timer output (shared as 14-bit PWM output). 8-bit timer output.
ANI0 to ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VSS IC
Input Input -- -- Input Input -- Input -- -- -- --
Input -- -- -- -- -- --
P10 to P17 -- -- -- -- -- -- P04 -- -- -- --
Subsystem clock oscillation crystal connection.
Input --
Positive power supply. Ground potential. Internal connection. Connected to VSS directly.
-- -- --
12
mPD78011B, 78012B, 78013, 78014
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 31. For the input/output circuit configuration of each type, see Fig. 3-1. Table 3-1 Input/Output Circuit Type of Each Pin (1/2)
Input/output Circuit Type 2 8-A
Pin Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60 to P63 P64/RD P65/WR P66/WAIT P67/ASTB
I/O Input Input/output
Recommended Connection when Not Used Connected to VSS . Input Output : Connected to VSS . : Leave open.
16 11 8-A 5-A 8-A 5-A 8-A 10-A
Input Input/output Input/output
Connected to VSS . Input Output Input Output : Connected to VDD or VSS . : Leave open. : Connected to VDD or VSS . : Leave open.
5-A
Input/output
Input Output
: Connected to VDD or VSS . : Leave open.
8-A
5-A
5-E 5-A 13-B 5-A
Input/output
Input Output Input Output
: Connected to VDD or VSS . : Leave open. : Connected to VDD or VSS . : Leave open.
Input/output
13
mPD78011B, 78012B, 78013, 78014
Table 3-1 Input/Output Circuit Type of Each Pin (2/2)
Pin Name RESET XT2 AVREF AVDD AVSS IC 2 16 -- Input/Output Circuit Type Input -- I/O -- Leave open. Connected to VSS . Connected to VDD . Connected to VSS . Connected to VSS directly. Recommended Connection when Not Used
14
mPD78011B, 78012B, 78013, 78014
Fig. 3-1 Pin Input/Output Circuits
Type 2 Type 10-A
pullup enable
V DD P-ch V DD
IN
data open drain output disable
P-ch IN / OUT N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-A
pullup enable V DD data output disable input enable
V DD P-ch
Type 11
pullup enable data
V DD P-ch V DD P-ch IN / OUT N-ch P-ch + - N-ch VREF (Threshold Voltage)
P-ch IN / OUT N-ch
output disable Comparator
input enable
Type 5-E
pullup enable data output disable
V DD P-ch V DD P-ch IN / OUT N-ch
Type 13-B
Mask Option data output disable N-ch V DD RD P-ch
V DD IN / OUT
Middle-High Voltage Input Buffer
Type 8-A
pullup enable V DD data output disable
V DD P-ch
Type 16
feedback cut-off P-ch
P-ch IN / OUT N-ch
XT1
XT2
15
mPD78011B, 78012B, 78013, 78014
4. MEMORY SPACE
The memory map of mPD78011B/78012B/78013/78014 is shown in Fig 4-1.
Fig.4-1 Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 Bits FF00H FEFFH FEE0H FEDFH General Registers 32 x 8 Bits
Internal High-Speed RAM*
mmmmH mmmmH-1 Use Prohibited Data Memory Space FAE0H FADFH FAC0H FABFH FA80H FA7FH Program Memory Space nnnnH+1 nnnnH Buffer RAM 32 x 8 Bits
nnnnH Program Area 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 0080H 007FH CALLT Table Area 0040H 003FH Internal ROM* Vector Table Area 0000H
0000H
Remarks
Shaded area indicates internal memory.
* Intermal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Product Name mPD78011B mPD78012B mPD78013 mPD78014 Intenal ROM End Address nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Internal High-Speed RAM StartAddress mmmmH FD00H
16
mPD78011B, 78012B, 78013, 78014
5
5.1
PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS
The I/O port has the following three types * CMOS input (P00, P04) * CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67) * N-ch open-drain input/output(15V withstand voltage) (P60 to P63) Total :2 : 47 :4 : 53
Table 5-1 Functions of Ports
Port Name Port 0 Pin Name P00, P04 P01 to P03 Port 1 Port 2 Port 3 Port 4 P10 to P17 P20 to P27 P30 to P37 P40 to P47 Dedicated Input port Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified in 8-bit units. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. LED can be driven directly. N-ch open-drain input/output port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Function
Port 5
P50 to P57
Port 6
P60 to P63
P64 to P67
Caution
When pull-up resistors are not used (specified by mask option), low-level input leak current increases with - 200 mA (MAX.) under either of the following conditions. 1 When the external device expansion function is used and a low-level is input to the pin. 2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode register (PM6).
17
mPD78011B, 78012B, 78013, 78014
5.2
CLOCK GENERATOR
There are two types of clock generator: main system clock and subsystem clock. The instruction exection time can be changed. * 0.4ms/0.8ms/1.6ms/3.2ms/6.4ms (Main system clock: at 10.0 MHz operation) * 122ms (Subsystem clock: at 32.768 KHz operation)
Fig. 5-1 Clock Generator Block Diagram
XT1/P04 XT2
Subsystem Clock Osicillator
fXT
Watch Timer Clock Output Function Prescaler
X1 X2
Main System Clock Osicillator
fX
Prescaler
Clock to Peripheral Hardware fX 24
fX 2 STOP
fX 22
fX 23
Selector
Standby Control Circuit
Wait Control Circuit
CPU Clock (fCPU)
INTP0 Sampling Clock
18
mPD78011B, 78012B, 78013, 78014
5.3 TIMER/EVENT COUNTER The following five channels are incorporated in the timer/event counter. * * * * 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : 1 channel 2 channels 1 channel 1 channel
Table 5-2 Types and Features of Timer/Event Counter
16-bit Timer/Event Counter Type Interval timer Externanal event counter Functions Timer output PWM output Pulse width mesurement Sqare wave output Interrupt request 1 channel 1 channel 1 output 1 output 1 input 1 output 2 8-bit Timer/Event Counter 2 channels 2 channels 2 outputs - - 2 outputs 2
Watch Timer 1channel - - - - - 2
Watchdog Timer 1 channel - - - - - 1
19
mPD78011B, 78012B, 78013, 78014
Fig. 5-2 16-bit Timer/Enent Counter Block Diagram
Internal Bus
16-Bit Compare Register (CR00) PWM Pulse Output Control Circuit 16-Bit Timer Register (TM0) Clear Selector Output Control Circuit
INTTM0
Match
TO0/P30
fX/2 fX/22 fX/23 TI0/INTP0/P00
Edge Detection Circuit Selector
INTP0 16-Bit Capture Register (CR01)
Internal Bus
Fig. 5-3 8-bit Timer/Enent Counter Block Diagram
Internal Bus INTIM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector
Match
Output Control Circuit
TO2/P32 INTTM2
fX/22-fX/210 fX/212 TI1/P33
Selector 8-Bit Timer Register 1 (TM1) Clear Selector
8-Bit Timer Register 2 (TM2) Clear
fX/22-fX/210 fX/2
12
Selector Selector Output Control Circuit Internal Bus
TI2/P34
TO1/P31
20
mPD78011B, 78012B, 78013, 78014
Fig. 5-4 Watch Timer Block Diagram
fX/28
Selector Prescaler
Selector
5-Bit Counter
fW 214
Selector INTWT
fXT fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
fW 213
Selector
INTTM3
Fig. 5-5 Watchdog Timer Block Diagram
fX 24 fX 25 fX 26 fX 27
Prescaler
fX 28
fX 29
fX 210
fX 212
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
21
mPD78011B, 78012B, 78013, 78014
5.4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output. * 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation) * 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Fig. 5-6 Clock Output Control Block Diagram
fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fXT
Selector Synchronization Circuit Output Control Circuit PCL/P35
5.5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for buzzer output. * 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Fig. 5-7 Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212
Selector Output Control Circuit BUZ/P36
22
mPD78011B, 78012B, 78013, 78014
5.6 A/D CONVERTER The A/D converter has on-chip eight 8-bit resolution channels. There are the following two method to start A/D conversion. * Hardware starting * Software starting
Fig. 5-8 A/D Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approxmation Register (SAR) AVSS Selector Tap Selector Sample & Hold Circuit Voltage Comparator AVDD AVREF
INTP3/P03
Falling Edge Detector
Control Circuit
INTAD INTP3
A/D Conversion Result Register (ADCR)
Internal Bus
23
mPD78011B, 78012B, 78013, 78014
5.7 SERIAL INTERFACES There are two on-chip clocked serial interfaces as follows. * Serial Interface channel 0 * Serial Interface channel 1 Table 5-3 Type and Function of Serial Interface
Function 3-wire serial I/O mode 3-wire serial I/O mode with automatic data transmit /receive function SBI (Serial Bus Interface) mode 2-wire serial I/O model (MSB-first)
l l
Serial Interface Channel 0 (MSB/LSB-first switchable)
l l
Serial Interface Channel 1 (MSB/LSB-first switchable) (MSB/LSB-first switchable)
-
(MSB-first)
- -
-
Fig. 5-9 Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector Serial I/O Shift Register 0 (SIO0) Output Latch
SO0/SB1/P26
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Counter
Busy/Acknowlede Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fx/22-fx/29
Serial Clock Control Circuit Selector
TO2
24
mPD78011B, 78012B, 78013, 78014
Fig. 5-10 Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer RAM
SI1/P20
Serial I/O Shift Register 1 (SIO0)
SO1/P21
STB/P23
BUSY/P24
Handshake Control Circuit
SCK/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
fX/22 - fX/29
Serial Clock Control Circuit Selector
TO2
25
mPD78011B, 78012B, 78013, 78014
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS There are the 14 interrupt functions of 3 different kind as shown below. * Non-maskable interrupt * Maskable interrupt * Software interrupt :1 : 12 :1
Table 6-1 Interrupt Source List
Interrupt Source Interrupt Type Default Priority*1 Name INTWDT Trigger Watchdog timer overflow (with nonmaskable interrupt selected) Watchdog timer overflow (with interval timer selected) Pin input edge detection External 0006H 0008H 000AH 000CH Serial interface channel 0 transfer end Serial interface channel 1 transfer end Reference time interval signal from watch timer 16 bit timer/event counter match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation A/D converter conversion end BRK instruction execution Internal Internal 000EH 0010H 0012H B Internal /External Vector Table Address Basic*2 Configuratin Type A
Non-maskable
---
Internal
0004H
Maskable
0
INTWDT
B
1 2 3 4 5 6 7
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3
C D
8
INTTM0
0014H
9
INTTM1
0016H
10
INTTM2
0018H
11 Software ---
INTAD BRK
001AH 003EH E
* 1. The default pririty is the priority applicable when more than one maskable interrupt is generated. 0 is the highest priority and 11, the lowest. 2. Basic configuration types A to E correspond to A to E on the next page.
26
mPD78011B, 78012B, 78013, 78014
Fig. 6-1 Basic Interrupt Function Configuration (1/2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal Maskable Interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
27
mPD78011B, 78012B, 78013, 78014
Fig. 6-1 Basic Interrupt Function Configuration (2/2) (D) External Maskable Interrupt (Except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E)
Software Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Remarks
1. 2. 3. 4. 5.
IF IE ISP MK PR
: Interrupt request flag : Interrupt enable flag : In-service priority flag : Interrupt mask flag : Priority spcification flag
28
mPD78011B, 78012B, 78013, 78014
6.2 TEST FUNCTIONS There are two test functions as shown in Table 6-2.
Table 6-2 Test Source List
Test Source Internal/External Name INTWT INTPT4 Trigger Watch timer overflow Port 4 falling edge detection Internal External
Fig. 6-2 Test Function Basic Configuration
Internal Bus
MK
Test Input
IF
Standby Release Signal
Remarks
1. 2.
IF : Test input flag MK : Test mask flag
29
mPD78011B, 78012B, 78013, 78014
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode. : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock.
* STOP mode
Fig. 8-1 Standby Functions
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation* HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply to CPU is stopped, oscillation)
HALT Mode* (Clock supply to CPU is stopped, oscillation)
* The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program.
9. RESET FUNCTIONS
There are the following two reset methods. * External reset input by RESET pin. * Internal reset by watchdog timer runaway time detection.
30
mPD78011B, 78012B, 78013, 78014
10. INSTRUCTION SET
(1) 8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP r1 sfr sadder MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !adder16 PSW MOV MOV MOV PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL+byte] [HL+B] [HL+C] X C MULU DIVUW MOV MOV MOV DBNZ INC DEC DBNZ MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A r* sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC $adder16 1 None
*
Except r=A
31
mPD78011B, 78012B, 78013, 78014
(2) 16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW* INCW, DECW PUSH, POP sfrp sadderp !adder16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #byte AX rp* sfrp saddrp !addr16 SP None
*
Only when rp=BC, DE, HL.
(3) Bit Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit CY $addr16 None
32
mPD78011B, 78012B, 78013, 78014
(4) Call Instruction/Branch Instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand AX 1st Operand Basic instruction BR CALL, BR CALLF CALLT BR, BC, BNC, BZ, BNZ Compound instruction BT, BF, BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
(5) Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
33
mPD78011B, 78012B, 78013, 78014
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVREF AVSS Input voltage VI1 VI2 Output voltage Analog input voltage Output current high IOH VAN VO P10 to P17 1 pin P10 to P17, P20 to P27, P30 to P37 total P01 to P03, P40 to P47, P50 to P57, P60 to P67 total Output current low 1 pin Effective value P40 to P47, P50 to P55 total Peak value Effective value P01 to P03, P56, P57, IOL* P60 to P67 total P01 to P03, P64 to P67 total Effective value Peak value Effective value 70 50 20 50 20 -40 to +85 mA mA mA mA mA C Peak value 15 100 70 100 mA mA mA mA Peak value Analog input pin P00 to P04, P10 to P17, P20 to P27, P30 toP37 P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2 P60 to P67 Open-drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS -0.3 to AVREF + 0.3 -10 -15 -15 30 V V V mA mA mA mA Test Conditions Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to VDD + 0.3 Unit V V V V V
P10 to P17, P20 to P27, P30 to P37 Peak value total Operating temperature Storage temperature Topt Tstg Effective value
-65 to +150
C
* Effective value should be calculated as follows: [Effective value] = [Peak value] duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
34
mPD78011B, 78012B, 78013, 78014
Capacitance ( Ta = 25 C, VDD = VSS = 0 V )
Parameter Input capacitance I/O capacitance f=1 MHz Unmeasured CIO pins returned to 0 V Symbol CIN Test Conditions f=1 MHz Unmeasured pins returned to 0 V P01 to P03, P10 to P17, P20 to P27, P30 toP37, P40 toP47, P50 to P57, P64 to P67 P60 to P63 20 pF 15 pF MIN. TYP. MAX. 15 Unit pF
Remarks
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics ( Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Ceramic resonator Recommended Circuit Parameter Test Conditions MIN. TYP. MAX. Unit
X1
X2
VSS R1
Oscillator frequency (fX) *1
VDD = Oscillator voltage range
1
10
MHz
C1
C2
Oscillation stabilization time *2
After VDD reaches oscillator voltage range MIN. 4 ms
Crystal resonator
X1
X2
VSS
Oscillator frequency (fX) *1 VDD = 4.5 to 6.0 V 1 8.38 10 MHz
C1
C2
Oscillation stabilization time *2
10 ms 30
External clock
X1 input
X1
X2
1.0
frequency (fX) *1
10.0
MHz
X1 input mPD74HCU04 high/low level width (tXH , tXL) 42.5 500 ns
* 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release.
Caution
1. When using the main system clock oscillator, wirinin the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. l l l l l l Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillator capacitor groundshould be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.
35
mPD78011B, 78012B, 78013, 78014
Subsystem Clock Oscillation Circuit Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Recommended Circuit Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal resonator
XT1 XT2
VSS R2
Oscillator frequency (fXT) *1 VDD = 4.5 to 6.0 V
32
32.768
35
kHz
C3
C4
Oscillation stabilization time *2
1.2
2 10
s
External clock
XT1 input
XT1
XT2
frequency (fXT) *1
32
100
kHz
XT1 input high/low level width (tXTH , tXTL) 5 15 ms
* 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Caution 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. l l l l l l Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock. Particular care is therefore required with the wiring method when the subsystem clock is used.
36
mPD78011B, 78012B, 78013, 78014
Recommended Oscillation Circuit Constant Main system clock: Ceramic resonator (Ta = -40 to +85 C) mPD78011B, 78012B
Frequency Product Name (MHz) C1 (pF) Murata Mfg. Co., Ltd. CSB1000J CSBJ CSA. MK CSA. MG 1.00 1.01 to 1.25 1.26 to 1.79 100 100 100 100 C2 (pF) 100 100 100 100 Built-in 30 Built-in 30 Built-in 30 Built-in R1 (kW) 6.8 4.7 0 0 0 0 0 0 0 0 0 MIN. (V) 2.9 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.9 2.9 MAX. (V) 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 Recommended Circuit Constant Oscillator Voltage Range
Manufacture
1.80 to 2.44
CST. MG CSA. MG Built-in 30
2.45 to 4.18
CST. MGW CSA. MG Built-in 30
4.19 to 6.00
CST. MGW CSA. MT Built-in 30
6.01 to 10.0
CST. MTW Kyocera KBR-4.19MWS 4.19 KBR-4.19MKS KBR-4.19MSA 4.19 PBRC4.19A KBR-10.0M KBR-1000F 1.00 KBR-1000Y 100 100 2.2 2.7 6.0 10.0 33 33 - 2.8 6.0 33 33 - 2.7 6.0 - - - 2.7 6.0 Built-in
mPD78013, 78014
Recommended Circuit Constant Manufacture Product Name CSB1000J CSBJ CSA. MK CSA. MG Frequency 1.00 1.01 to 1.25 1.26 to 1.79 (MHz) C1 (pF) 100 100 100 100 C2 (pF) 100 100 100 100 Built-in 30 Built-in 30 Built-in 30 Built-in R1 (kW) 6.8 4.7 0 0 0 0 0 0 0 0 0 Oscillator Voltage Range MIN. (V) 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 MAX. (V) 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0
Murata Mfg. Co., Ltd.
1.80 to 2.44
CST. MG CSA. MG Built-in 30
2.45 to 4.18
CST. MGW CSA. MG Built-in 30
4.19 to 6.00
CST. MGW CSA. MT Built-in 30
6.01 to 10.0
CST. MTW Built-in
Remarks
, . , . indicate frequency.
37
mPD78011B, 78012B, 78013, 78014
Subsystem clock: Cristal resonator (Ta = -40 to + 60 C) mPD78011B, 78012B
Recommended Frequency Manufacture Products (MHz) C3 (pF) C4 (pF) R2 (ky) MIN. (V) MAX. (V) Circuit Constant Oscillator Voltage Range
Daishinku
DT-38 (1TA632 E00, load capacitance 6.3 pF) 32.768 8 8 100 2.7 6.0
mPD78013, 78014
Recommended Frequency Manufacture Product Name (MHz) C3 (pF) C4 (pF) R2 (ky) MIN. (V) MAX. (V) Circuit Constant Oscillator Voltage Range
Daishinku
DT-38 (1TA632 E00, load capacitance 6.3 pF) 32.768 12 12 100 2.7 6.0
38
mPD78011B, 78012B, 78013, 78014
DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Input voltage high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Test Conditions P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 X1, X2 VDD = 4.5 to 6.0 V XT1/P04, XT2 VDD-0.3 Input voltage low VIL1 VIL2 VIL3 P10 to P17, P21, P23, P30 to P32, P35 to P37 P40 to P47, P50 to P57, P64 to P67 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET VDD = 4.5 to 6.0 V P60 to P63 0 VIL4 VIL5 X1, X2 VDD = 4.5 to 6.0 V XT1/P04, XT2 0 Output voltage high Output voltage low VOL1 P01 to P03, P10 to P17, P20 to P27 P30 to P37, P40 to P47, P64 to P67 VDD = 4.5 to 6.0 V, IOL = 1.6 mA VDD = 4.5 to 6.0 V, open-drain pulled-up (R = 1 Ky ) 0.4 V VOH1 IOH = -100 mA P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA VDD-0.5 0.4 2.0 V V VDD = 4.5 to 6.0 V,IOH = -1 mA VDD-1.0 0.3 V V 0 0 0.2 VDD 0.4 0.4 V V V 0 0 0 VDD 0.3 VDD 0.2 VDD 0.3 VDD V V V V Open-drain MIN. 0.7 VDD 0.8 VDD 0.7 VDD VDD-0.5 VDD-0.5 TYP. MAX. VDD VDD 15 VDD VDD Unit V V V V V
VOL2
SB0, SB1, SCK0
0.2 VDD
V
VOL3 Input leakage current high
IOL = 400 mA P00 P20 P40 P60 to to to to P03, P10 to P17, P27, P30 to P37, P47, P50 to P57, P67 RESET
0.5
V
ILIH1
VIN = VDD
3
mA
ILIH2 ILIH3 Input leakage current low VIN = 15 V
X1, X2, XT1/P04, XT2 P60 to P63 P00 P20 P40 P64 to to to to P03, P10 to P17, P27, P30 to P37, P47, P50 to P57, P67 RESET
20 80
mA mA
ILIL1 VIN = 0 V ILIL2 ILIL3
-3
mA
X1, X2, XT1/P04, XT2 P60 to P63 Other *1 than above
-20 -200 -3*2
mA mA mA
* 1. When memory expansion mode is used by the memory expansion mode register (MM) with no on-chip pullup resistor by mask option. 2. When pull-up resistors are not used (specified by mask option), the low-level input leakage current increases with -200 mA (MAX.) under either of the following conditions.
1 2
When the external device expansion function is used and a low level is input to the pin. During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode registor (PM6). The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Remarks
39
mPD78011B, 78012B, 78013, 78014
DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Output leakage current high Output leakage current low Mask option pullup resister Software pullup resister R2 VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 8.38 MHz Crystal oscillation operating mode 8.38 MHz Crystal oscillation HALT mode 32.768 kHz Crystal oscillation operating mode 32.768 kHz Crystal oscillation HALT mode XT1 = 0 V STOP mode When feedback resister is used XT1 = 0 V STOP mode When feedback resister is unused 2.7 V VDD < 4.5 V 20 500 kW -3 mA Symbol ILOH1 VOUT = VDD Test Conditions MIN. TYP. MAX. 3 Unit mA
ILOL
VOUT = 0 V
R1
VIN = 0 V, P60 to P63
20
40
90
kW
4.5 V VDD 6.0 V
15
40
90
kW
Power supply current *5
VDD = 5.0 V 10 % *3 VDD = 3.0 V 10 % *4 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 %
7.5 0.8 1.4 550 60 35 25 5 1 0.5 0.1 0.05
22.5 2.4 4.2 1650 120 70 50 10 20 10 20 10
mA mA mA
mA mA mA mA mA mA mA mA mA
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
* 3. Operating in high-speed mode (when set the processor clock control register to 00H). 4. Operating in low-speed mode (when set the processor clock control register to 04H). 5. AVREF current and port current are excluded. Remarks The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
40
mPD78011B, 78012B, 78013, 78014
AC Characteristics (1) Basic Operation (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Cycle time (Min. instruction execution time) Operationg on subsystem clock TI input frequency TI input high/ low-level width Interrupt input high/low-level width tINTH INTP1 to INTP3 tINTL KR0 to KR7 RESET low level width tRSL 10 10 10 fTI 0 tTIH tTIL INTP0 VDD = 4.5 to 6.0 V 100 1.8 8/fsam* 275 kHz ns ms ms ms ms ms VDD = 4.5 to 6.0 V 40 0 122 125 4 ms MHz TCY Symbol Test Conditions Operating on main system clock VDD=4.5 to 6.0 V MIN. 0.4 0.96 TYP. MAX. 64 64 Unit ms ms
* In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1, fX/64 and fx/128 (when N= 0 to 4).
41
mPD78011B, 78012B, 78013, 78014
mPD78011B, 78012B, 78013, 78014 TCY vs VDD (At main system clock operation)
60
mPD78P014 (Reference) TCY vs VDD (At main system clock operation)
60
Cycle Time TCY (ms)
10 Operation Guaranteed Range
Cycle Time TCY (ms)
10 Operation Guaranteed Range
2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply Voltage VDD [V]
0 1 2 3 4 5 6 Supply Voltage VDD [V]
Remarks
indicates Ta=-40 to +40 C indicates Ta=-40 to +80 C
Caution
The operation guaranteed range of the mPD78011B, 78012B, 78013 and 78014 differs from that of the mPD78P014.
42
mPD78011B, 78012B, 78013, 78014
(2) Read/Write Operation (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RDO tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAITO input time from RDO tRDWT1 tRDWT2 WAITO input time from WRO WAIT low-level width Write data setup time Write data hold time WR low-level width RDO delay time from ASTBO WRO delay time from ASTBO ASTB* delay time from RD* in external fetch Address hold time from RD* in external fetch Write data output time from RD* WRO delay time from write data tWDWR 0.5tCY-170 Address hold time from WR* tWRADH tCY RD* delay time from WAIT* WR* delay time from WAIT* tWTRD tWTWR 0.5tCY 0.5tCY tCY+100 2.5tCY+80 2.5tCY+80 ns ns ns VDD =4.5 to 6.0 V tCY 0.5tCY tCY+60 ns ns tRDWD VDD = 4.5 to 6.0 V 10 0.5tCY-120 0.5tCY ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5+2n)tCY +10 100 5 (2.5+2n)tCY -20 0.5tCY-30 1.5tCY -30 tCY-10 tCY+40 0 (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY 5 Load resistor * 5 kW Test Conditions MIN. 0.5tCY 0.5tCY-30 10 (2+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
tCY
tCY+50
ns
Remarks
1. 2. 3.
tCY = TCY/4 n indicates number of waits. CL = 100 pF (CL indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/ RD, P65/WR, P66/WAIT,P67/ASTB pins).
43
mPD78011B, 78012B, 78013, 78014
(3) Serial Interface (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter SCK cycle time
Symbol
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
Unit ns ns ns ns ns ns
tKCY1
SCK high/low-level width
tKH1 tKL1
VDD = 4.5 to 6.0 V
tKCY1/2-50 tKCY1/2-150 100 400 VDD = 4.5 to 6.0 V 300 1000
SI setup time (to SCK*) SI hold time (from SCK*) SO output delay time from SCKO
tSIK1 tKSI1 tKSO1
C = 100 pF*
ns ns
* C is the load capacitance of SO output line.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter SCK cycle time
Symbol
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
Unit ns ns ns ns ns ns
tKCY2
SCK high/low-level width
tKH2 tKL2
VDD = 4.5 to 6.0 V
400 1600 100 400 VDD = 4.5 to 6.0 V 300 1000
SI setup time (to SCK*) SI hold time (from SCK*) SO output delay time from SCKO
tSIK2 tKSI2
ns ns
tKSO2
C = 100 pF*
H H
SCK rise, fall time (When serial interface channel 0 is used) tR2 tF2
When external device expansion function is used When 16-bit timer output function is When external device expansion used When 16-bit timer output function is not used
160
ns
700
ns
H
function is not used
1000
ns
H H
SCK rise, fall time (When serial interface channel 1 is used) tF2 tR2
When external device expansion function is used When external device expansion function is not used 1000 ns 160 ns
* C is the load capacitance of SO output line.
44
mPD78011B, 78012B, 78013, 78014
(c) SBI mode (SCK... Internal clock output)
Parameter SCK cycle time Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 800 3200 SCK high/low-level width TYP. MAX. Unit ns ns ns ns ns ns
tKCY3 tKH3 tKL3
VDD = 4.5 to 6.0 V
tKCY3/2-50 tKCY3/2-150
SB0, SB1 setup time (to SCK*)
VDD = 4.5 to 6.0 V
100 300
tSIK3
SB0, SB1 hold time (from SCK*) SB0, SB1 output delay time from SCKO
tKSI3
tKCY3/2
ns
R = 1 kW ,
VDD = 4.5 to 6.0 V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
tKSO3
C = 100 pF*
SB0, SB1O from SCK* SCKO from SB0, SB1O SB0, SB1 high-level width SB0, SB1 low-level width
tKSB tSBK tSBH tSBL
* R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
45
mPD78011B, 78012B, 78013, 78014
(d) SBI mode (SCK... External clock output)
Parameter SCK cycle time Symbol Test Conditions VDD = 4.5 to 6.0 V tKCY4 3200 SCK high/low-level width tKH4 tKL4 SB0, SB1 setup time (to SCK*) tSIK4 300 ns VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. Unit ns
SB0, SB1 hold time (from SCK*) SB0, SB1 output delay time from SCKO
tKSI4
tKCY4/2
ns
R = 1 kW , tKSO4 C = 100 pF* tKSB tSBK tSBH tSBL
VDD = 4.5 to 6.0 V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
SB0, SB1O from SCK* SCKO from SB0, SB1O SB0, SB1 high-level width SB0, SB1 low-level width
H H
SCK rise, fall time
When external device expansion function is used When 16-bit timer output function is When external device expansion function is used When 16-bit timer output function is not used
160
ns
tR4 tF4
700
ns
H
not used
1000
ns
* R and C are the load resistors and load capacitance of the SB0 and SB1 output line. (e) 2-wire serial I/O mode (SCK... Internal clock output)
Parameter SCK cycle time Symbol tKCY5 Test Conditions VDD = 4.5 to 6.0 V MIN. 1600 3800 SCK high-level width SCK low-level width SB0, SB1 setup time (to SCK*) SB0, SB1 hold time (from SCK*) SB0, SB1 output delay time from SCKO tKSO5 C = 100 pF* 0 1000 ns tKSI5 600 ns tKH5 tKL5 R = 1 kW, C = 100 pF* tKCY5/2-50 tKCY5/2-50 TYP. MAX. Unit ns ns ns ns
tSIK5
300
ns
R = 1 kW,
VDD = 4.5 to 6.0 V
0
250
ns
* R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
46
mPD78011B, 78012B, 78013, 78014
(f)
2-wire serial I/O mode (SCK... External clock input)
Parameter Symbol Test Conditions VDD = 4.5 to 6.0 V tKCY6 3800 ns ns ns ns MIN. 1600 TYP. MAX. Unit ns
SCK cycle time
SCK high-level width SCK low-level width SB0, SB1 setup time (to SCK*) SB0, SB1 hold time (from SCK*) SB0, SB1 output delay time from SCKO
tKH6 tKL6 tSIK6
650 800 100
tKSI6
tKCY6/2
ns
R = 1 kW, tKSO6 C = 100 pF*
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
SCK rise, fall time
When external device expansion function is used When 16-bit timer When external tF6 device expansion function is not used output function is used When 16-bit timer output function is not used
H
160 ns
tR6
H
700 ns
H
1000 ns
* R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
47
mPD78011B, 78012B, 78013, 78014
(g) 3-wire serial I/O mode with automatic transmit/receive function (SCK...Internal clock output)
Parameter SCK cycle time
Symbol
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
UNIT ns ns ns ns
tKCY7
SCK high/low-level width
tKH7 tKL7
VDD = 4.5 to 6.0 V
tKCY7/2-50 tKCY7/2-150
SI setup time (to SCK*) tSIK7 100 ns
SI hold time (from SCK*) tKSI7 400 ns
SO output delay time from SCKO tKSO7 C = 100 pF*
VDD = 4.5 to 6.0 V
300 1000
ns ns ns
STB* from SCK* Strobe signal high-level width
tSBD
400
tKCY7
tSBW
tKCY7-30
tKCY7+30
ns
Busy signal setup time (to busy signal detection timing)
tBYS
100
ns
Busy signal hold time (from busy signal detection timing) SCKO from busy inactive
tBYH
100
ns
tSPS
2tKCY7
ns
* C is the load capacitance of the SO output line.
48
mPD78011B, 78012B, 78013, 78014
(h) 3-wire serial I/O mode with automatic transmit/receive function (SCK...External clock input)
Parameter SCK cycle time
Symbol
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
UNIT ns ns ns ns
tKCY8
SCK high/low-level width
tKH8 tKL8
VDD = 4.5 to 6.0 V
400 1600
SI setup time (to SCK*) tSIK8 100 ns
SI hold time (from SCK*) tKSI8 400 ns
SO output delay time from SCKO tKSO8 C = 100 pF*
VDD = 4.5 to 6.0 V
300 1000
ns ns
SCK rise, fall time tR8 tF8
When external device expansion function function is used When external device expansion function is not used
H
160 ns
H
1000 ns
* C is the load capacitance of the SO output line.
49
mPD78011B, 78012B, 78013, 78014
(4) A/D converter characteristics (Ta = -40 to +85 C, AVDD = VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error* Conversion time Sampling time Analog input voltage Reference voltage AVREF current tCONV tSAMP VIAN AVREF AIREF 19.1 24/fx AVSS 2.7 0.5 AVREF AVDD 1.5 Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 200 Unit bit % ms ms V V mA
* Overroll error excluding quantization error (1/2 LSB). It is indicated as a ratio to the full-scale value.
50
mPD78011B, 78012B, 78013, 78014
AC Timing Test Point (Excluding X1, XT1 Input)
Clock Timing
1/fX
tXL
tXH VDD - 0.5 V 0.4V
X1 Input
1/fXT
tXTL
tXTH VDD - 0.5 V 0.4V
XT1 Input
TI Timing
1/fTI
tTIL TI0-TI2
tTIH
51
mPD78011B, 78012B, 78013, 78014
Read/Write Operation External fetch (No wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
52
mPD78011B, 78012B, 78013, 78014
External data access (No wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
RD tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
WR tASTWR tWRL1
External data access (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD RD tRDL2 tRDWD WR tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
53
mPD78011B, 78012B, 78013, 78014
Serial Transfer Timing 3-wire serial I/O m ode:
tKCY 1,2
tKL1,2 tR2
tKH1,2 tF2
H
SCK tSIK1,2 tKSI1,2
SI tKSO1,2
Input Data
SO
Output Data
SBI mode (Bus release signal transfer):
tKCY3,4 tKL3,4 tR4 tKH3,4 tF4
H
SCK tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4
SB0, SB1 tKSO3,4
SBI Mode (command signal transfer):
tKCY3,4 tKL3,4 tR4 tKH3,4 tF4
H
SCK tKSB tSBK tSIK3,4 tKSI3,4
SB0, SB1 tKSO3,4
54
mPD78011B, 78012B, 78013, 78014
2-wire serial I/O mode:
tKCY5,6 tKL5,6 tR6 SCK tSIK5,6 tKSO5,6 SB0, SB1 tKSI5,6 tKH5,6 tF6
H
3-wire serial I/O mode with automatic transmit/receive function:
SO
D2
D1
D0
D7
SI
D2 tSIK7,8 tKSO7,8
D1 tKSI7,8 tKH7,8
D0
D7
tF8
H
SCK tSBD tKL7,8 STB tKCY7,8 tR8 tSBW
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK
7
8
9* tBYS
10* tBYH
10+n* tSPS
1
BUSY (Active High)
* The signal is not actually driven low here; it is shown as such to indicate the timing.
55
mPD78011B, 78012B, 78013, 78014
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (Ta = -40 to +85 C)
Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR = 2.0 V Subsystem clock stop and feed-back resister disconnected Release signal set time Oscillation stabilization wait time Release by interrupt * ms tSREL tWAIT Release by RESET 0 218/fx ms ms 0.1 10 mA Symbol VDDDR Test Conditions MIN. 2.0 TYP. MAX. 6.0 Unit V
* In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/fx and 215/fx to 218/fx is possible. Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
56
mPD78011B, 78012B, 78013, 78014
Interrupt Input Timing
tINTL INTP0-INTP2 tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
57
m78011B, 78012B, 78013, 78014
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 8.38 MHz)
(Ta=25C)
10.0
5.0
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation)
1.0
0.5
Supply Current IDD [mA]
0.1 PCC=B0H 0.05
HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation)
0.01
0.005
f X =4.19MHz f XT=32.768kHz
0.001 0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
58
m78011B, 78012B, 78013, 78014
IDD vs VDD (Main System Clock: 4.19 MHz)
(Ta=25C)
10.0
5.0
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation)
1.0
0.5
Supply Current IDD [mA]
0.1 PCC=B0H 0.05
HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation)
0.01
0.005
f X =4.19MHz f XT=32.768kHz
0.001 0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
59
m78011B, 78012B, 78013, 78014
IDD vs fX (VDD = 3 V, Ta = 25 C)
5 PCC = 00H 4
Supply Current IDD [mA]
3 PCC = 01H
2
PCC = 02H PCC = 03H PCC = 04H HALT (X1 Oscillation)
1
0 0 1 2 3 4 5 6 7 8 9 Clock Oscillator Frequency fX [MHz] 10 11 12
IDD vs fX (VDD = 5 V, Ta = 25 C) 12 11 10 9 PCC = 00H Supply Current IDD [mA] 8 7 6 PCC = 01H 5 4 3 2 1 0 PCC = 02H PCC = 03H PCC = 04H HALT (X1 Oscillation)
0
1
2
3
4 5 6 7 8 9 Clock Oscillator Frequency fX [MHz]
10
11
12
60
m78011B, 78012B, 78013, 78014
VOL vs IOL (Port 0, 2 to 5, P64 to P67)
(Ta=25C) VDD=5 V VDD=6 V VDD=4 V VDD=3 V
30
Output Current Low IOL [mA]
20
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
(Ta=25C)
30 Output Current Low IOL [mA]
VDD=6 V VDD=5 V VDD=4 V
VDD=3 V
20
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
61
m78011B, 78012B, 78013, 78014
VOL vs IOL (P60 to P63)
(Ta=25C)
30
VDD=6 V
VDD=5 V
VDD=4 V
Output Current Low IOL [mA]
VDD=3 V 20
10
0 0 0.5 1.0 Output Voltage Low VOL [V]
VOH vs IOH (Port 0 to 5, P64 to P67)
(Ta=25C)
Output Current High IOH [mA]
-10
VDD=5 V VDD=4 V VDD=6 V VDD=3 V
-5
0 0 0.5 1.0
Output Voltage High VDD - VOH [V]
62
mPD78011B, 78012B, 78013, 78014
13. PACKAGE INFORMATION
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
Caution
Dimensions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
H
63
mPD78011B, 78012B, 78013, 78014
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
64 PIN PLASTIC QFP ( 14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15 +0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Caution 64
Dimensions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (2/2).
M
55
Q
mPD78011B, 78012B, 78013, 78014
DRAWINGS OF ES PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil)
64
33
1 A J I
32 K L
F D
H
B
NM C M 0~15
G
P64D-70-750A1 NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N MILLIMETERS 58.16 MAX. 1.521 MAX. 1.778 (T.P.) 0.46 0.05 0.8 MIN. 3.5 0.3 1.02 MIN. 3.14 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.05 0.25 INCHES 2.290 MAX. 0.060 MAX. 0.070 (T.P.) 0.018 0.002 0.031 MIN. 0.138 0.012 0.040 MIN. 0.124 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01
+0.002
65
mPD78011B, 78012B, 78013, 78014
DRAWINGS OF ES PRODUCT PACKAGES (2/2)
64 PIN CERAMIC QFP (14 x 14) (FOR ES)
A B
48 49
33 32
64 1
17 16
F
G
H
J K Q M
D
C
(Bottom View)
X64B-80A-1 INCHES 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (T.P.) 0.157+0.007 -0.006 0.01 0.119 MAX. 0.022 0.039 0.047
ITEM A B
MILLIMETERS 22.0 0.4 14.0 14.0 22.0 0.4 1.0 1.0 0.32 0.8 (T.P.) 4.0 0.15 0.25 3.0 MAX. 0.55 1.0 1.2
T
C D F G
U V
H J K M Q T U V
66
mPD78011B, 78012B, 78013, 78014
14. RECOMMENDED SOLDERING CONDITIONS
The mPD78011B/78012B/78013/78014 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IE-1207). For soldering methods and conditions other than those recommended below, contact our salespersonnel. Table 14-1 Surface Mounting Type Soldering Conditions (1) mPD78011BGC--AB8 : 64-Pin Plastic QFP (n14 mm) mPD78012BGC--AB8 : 64-Pin Plastic QFP (n14 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max. < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above) Number of times: Twice max. < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Pin temperature: 300C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol IR35-00-2
H
VPS
VP15-00-2
Pin part heating
--
(2) mPD78013GC--AB8 : 64-Pin Plastic QFP (n14 mm) mPD78014GC--AB8 : 64-Pin Plastic QFP (n14 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: Twice < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Solder bath temperature: 260C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120C max. (Package surface temperature) Pin temperature: 300C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Pin part heating
--
Caution
Use more than one soldering method should be avoided (except in the case of pin part heating). 67
mPD78011B, 78012B, 78013, 78014
Table 14-2 Insertion Type Soldering Conditions mPD78011BCW- mPD78012BCW- mPD78013CW- mPD78014CW-
Soldering Method Wave soldering (pin only) Pin part heating
: : : :
64-Pin Plastic Shrink DIP 64-Pin Plastic Shrink DIP 64-Pin Plastic Shrink DIP 64-Pin Plastic Shrink DIP
(750 mil) (750 mil) (750 mil) (750 mil)
Soldering Conditions Solder bath temperature: 260C max., Duration: 10 sec. max. Pin temperature: 300C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly.
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mPD78011B, 78012B, 78013, 78014
APPENDIX A. DEVEROPMENT TOOLS
The following development tools are available for system development using the mPD78011B, 78012B, 78013, 78014. Language Processing Software
RA78K/0*1, 2, 3 CC78K/0*1, 2, 3 DF78014*1, 2, 3 CC78K/0-L*1, 2, 3 78K/0 series common assembler package 78K/0 series common C compiler package mPD78014 subseries device file 78K/0 series common C compiler library source file
H
PROM Writting Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controller*1, 2 PROM programmer Programmer adapter connected to PG-1500
PG-1500 control program
Debugging Tool
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0*1, 2 SM78K/0*4, 5, 6 DF78014*1, 2, 4, 5 Socket to be mounted on user system board created for the 64-pin plastic QFP IE-78000-R screen debugger 78K/0 series common system simulator mPD78014 subseries device file 78K/0 series common in-circuit emulator 78K/0 series common break board mPD78002/78014 subseries evaluation emulation board Emulation probe common to mPD78244 subseries
H
Real-Time OS
RX78K/0*1, 2, 3 MX78K/0
*1, 2, 3, 6
78K/0 series common real-time OS 78K/0 series common OS
H
Fuzzy Inference Devleopment Support System
FE9000*1/FE9200*5 FT9080*1/FT9085*2 FI78K0*1, 2 FD78K0*1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
* 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM (PC DOSTM) based 3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM, (SunOSTM) based, EWS-4800 series (EWS-UX/V) based
H
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mPD78011B, 78012B, 78013, 78014
4. PC-9800 series (MS-DOS + WindowsTM) based 5. IBM PC/AT (PC DOS + Windows) based 6. Under development Remarks 1. 2. For development tools manufactured by a third party, see the "78K/0 Series Selection Guide" (IF1185). RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used in combination with DF78014.
H
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mPD78011B, 78012B, 78013, 78014
APPENDIX B. RELATED DOCUMENTS Device Related Documents
Document Name User's Manual 78K/0 Series User's Manual - Instruction Application Note Basic I Basic II Floating-Point Arithmetic Program Electronic Notebook Document No. (Japanese) IEU-780 IEU-849 IEA-715 IEA-740 IEA-718 IEA-744 Document No. (English) IEU-1314 IEU-1372 IEA-1288 IEA-1299 IEA-1289 IEA-1301
H
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78014-R-EM SD78K/0 Screen Debugger Basic Reference Document No. (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-805 EEU-852 EEU-816 Document No. (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1400 EEU-1414 EEU-1413
Caution
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
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mPD78011B, 78012B, 78013, 78014
Embedded Software Documents (User's Manual)
Document Name Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System - Translator Document No. (Japanese) EEU-829 EEU-862 Document No. (English) EEU-1438 EEU-1444
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Semiconductor Devices Quality Guarantee Guide Document No. (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document No. (English) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
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mPD78011B, 78012B, 78013, 78014
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function.
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mPD78011B, 78012B, 78013, 78014
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
FIP is a registered trademark of NEC Corporation. IEBus is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a tradmark of SPARC International, Inc. SunOS is a tradmark of Sun Microsystems, Inc.

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